Charge-Mode Parallel Architecture for Vector–Matrix Multiplication

An internally analog, externally digital architecture for parallel vector–matrix multiplication is presented. A threetransistor unit cell combines a single-bit dynamic random-access memory and a charge injection device binary multiplier and analog accumulator. Digital multiplication of variable resolution is obtained with bit-serial inputs and bit-parallel storage of matrix elements, by combining quantized outputs from multiple rows of cells over time. A prototype 512 128 vector–matrix multiplier on a single 3 mm 3 mm chip fabricated in standard 0.5m CMOS technology achieves 8-bit effective resolution and dissipates 0.5 pJ per multiply-accumulate.